2 Bit Comparator Verilog Code. The objective of this post is to understand how to model a 2 bit comparator and a 4 bit comparator in verilog. Verilog code for a comparator in this project a simple 2 bit comparator is designed and implemented in verilog hdl.
A1b1 a1 a0b1 b0 a1a0b1b0 which simplifies to. Even though it checks for 4 bit inputs the code. If both results from cmp 1bit are 1 eq 1 otherwise eq 0.
The minimized expressions obtained from k map tables for the outputs are used for vhdl coding of the comparator.
Output gt when a is greater than b output equ when a is equal to b output lt when a is less than b boolean output descriptions assign gt a 1 b 1 a 1 a 0 b 0 a 0 b 1 b 0 assign equ a 1 a 0 b 1 b 0 a 1 a 0 b 1 b 0 a 1 a 0 b 1 b 0 a 1 a 0 b 1 b 0 assign. Three output signals are a less b 1 if a b else 0 a equal b 1 if a b else 0 and a greater b 1 if a b else 0. A free and complete verilog course for students. Logic circuit for 1 bit comparator.
