2 To 1 Mux Logic Diagram. The data inputs of upper 8x1 multiplexer are i 15 to i 8 and the data inputs of lower 8x1 multiplexer are i 7 to i 0. The block diagram of 16x1 multiplexer is shown in the following figure.
Input d0 d1 s. Y d0 s d1 s. In 2 1 multiplexer there are only two inputs i e a 0 and a 1 1 selection line i e s 0 and single outputs i e y.
Where n number of input selector line.
The block diagram and the truth table of the 2 1 multiplexer are given below. Module m21 y d0 d1 s. There s no need for data type declaration in this modeling. The block diagram and the truth table of the 2 1 multiplexer are given below.
