And Gate Schematic In Cadence. Create their connection with the wire tool and add what will be the input and output pins of your and gate named and in a and in ba nd out andin the example below. Draw a schematic of a simple nand gate and simulate it.
Draw layout of a nand gate using cell library then run a design rule check drc extract run a layout versus schematic lvs and simulate the extracted circuit. Or the poly silicon of the gate and draw a wire to wherever you desire. Compare the schematic and extracted simulations.
With the 2x1and cell schematic generated you can now begin to design the and gate using components in the ece331 library.
Or the poly silicon of the gate and draw a wire to wherever you desire. Virtuoso layout editor is the layout editor of the cadence design tools. This time we will use a 20 2 sized p channel mosfet. Now to make a nor gate using 4 mosfets just like the nand gate.
