Clock Divider Vhdl. Usually the clock signal comes from a crystal oscillator on board. The frequency divider process lines 16 to 28 generates the 200hz signal by using a counter from 1 to 124999.
Clock divider is also known as frequency divider which divides the input clock frequency and produce output clock. Why 124999 and not 250000. The oscillator used on digilent fpga boards usually ranges from 50 mhz to 100 mhz.
For this case 125000 cycles active and 125000 cycles inactive.
Why 124999 and not 250000. Vhdl code consist of clock and reset input divided clock as output. One led on the cpld board is connected to the clock source which is running at about 130hz making the led appear to be switched on. We demonstrate that using an integer clock divider the vhdl design maintains the same timing performances of a design with the clock provided on a dedicated clock pin.
