Cmos Nand Gate Transistor. For 0 35µm process technology tox 7 6 10 9m ε ox 35 10 12f m. If both of the a and b inputs are high then both the nmos transistors bottom half of the diagram will conduct neither of the pmos transistors top half will conduct and a conductive path will be established between the output and vss ground bringing the output low.
If either input a or b is logic 0 at least one of the nmos transistors will be off breaking the path from y to ground. Tutorial on transistor sizing problem 1 static cmos logic. Cmos gate inputs are sensitive to static electricity.
If both of the a and b inputs are high then both the nmos transistors bottom half of the diagram will conduct neither of the pmos transistors top half will conduct and a conductive path will be established between the output and vss ground bringing the output low.
These devices are available from most semiconductor manufacturers such as fairchild semiconductor philips or texas instruments these are usually available in both through hole dil and soic format. Cmos logic gates are made of igfet mosfet transistors rather than bipolar junction transistors. Cmos gate inputs are sensitive to static electricity. All devices in this series are derived from the 2 input nand gate.
