D Flip Flop With Reset Schematic. They have individual data nd clock ncp set nsd and reset nrd inputs and complementary nq and nq outputs. The classic por power on reset circuit with a 74hc74 looks like.
The nand gates and not gates in the enable portion of the schematic can be combined into just nand gates i added the not gates to keep my schematic similar to yours. Simply for positive transition on clock signal if d 0 q 0 so flip flop is reset. The r1 c1 time constant is set to be significantly longer than the rise time of the power line typically 10 s of milliseconds.
Data at the nd input that meets the set up and hold time requirements on the low to high clock transition is stored in the flip flop and appears at the nq output.
The output changes state by signals applied to one or more control inputs. It is a circuit that has two stable states and can store one bit of state information. If d 1 q 1 so flip flop is set. The flip flop is a basic building block of sequential logic circuits.
