Flash Adc Block Diagram. Each comparator compares vin to a different reference voltage starting with vref 1 2 lsb. This type of analog to digital converter incorporates successive approximation algorithm to convert analog input to a digital binary code.
Turns out this is a perfect explanation of what i intend to build. Figure 1 block diagram of the proposed tiq based flash adc. 6 shows the block diagram of successive approximation adc which consists of comparator sar successive approximation register sample and hold circuit and dac.
The reference voltage for each comparator is one least significant bit lsb greater than the reference voltage for the comparator immediately below it.
The reference voltage for each comparator is one least significant bit lsb greater than the reference voltage for the comparator immediately below it. Visual sar adc block diagram. Turns out this is a perfect explanation of what i intend to build. Our friends over on wikipedia have a graphic block diagram for the sar adc.
