Frequency Doubler Circuit Using Flip Flop. Here is a frequency multiplier circuit using pll565. If you need a symmetrical output cascade two doublers followed by a divide by two using a j k flip flop.
The trouble with it is that it relies on propagation delays in delay chains in order to generate the doubled frequency. Circuit which will divide the input clock frequency by 2 4 or 8 times in fact any value to the power of 2 we want making a binary counter. And the output terminal should be the q terminal of the last j k flip flop.
The frequency in goes to one of the xor inputs.
The reference frequency in this circuit drives the input of an exclusive or gate xor gate u2 as well as the input to a delay circuit. Build 1 2n frequency dividers with j k flip flop i strongly recommend you to look back at figure 1. Consisting of r1 c1 and comparator u1 the delay circuit drives the xor gate s second input. Finally the output of the doubler is taken from the xor gate.
