Nand Gate Cmos. Simple rule for wiring up mosfets. All inputs and outputs are buffered.
The truth table for the simple two input nand gate is given in table 6 1. There are two nmos transistors in series at the bottom and two parallel pmos transistors on top. Spring 2010 eecs150 lec8 cmos page transistor level logic circuits nfet is used only to pass logic zero.
The output terminal is connected to the supply voltage v dd and the output will be high.
The standard 4000 series cmos ic is the 4011 which includes four independent two input nand gates. The two input nand2 gate shown on the left is built from four transistors. A basic cmos structure of any 2 input logic gate can be drawn as follows. Spring 2010 eecs150 lec8 cmos page transistor level logic circuits nfet is used only to pass logic zero.
