Nand Gate Pin Diagram. Thus its output is complement to that of an and gate. The input pins are 1 2 4 5 9 10 12 13 and the output pins are 3 6 8 11.
In other words nand gate is an inversion of and gate. Iec logic symbol fig 3. If you see a transistor level logic diagram cd4011 consists of nmos and pmos transistors and logic for this high operation nand gate is based on not and nor gates.
The output voltage of the ic on the pin y will be equal to the operating voltage of the ic.
In other words nand gate is an inversion of and gate. The input pins are 1 2 4 5 9 10 12 13 and the output pins are 3 6 8 11. The typical operating voltage of the ic is 5v. The cd4011 ic contains four independent nand gates.
