Pipeline Adc Block Diagram. Two bits are required to obtain 1 5 bits and therefore 18 bits of raw output are available for digital error correction. The residual to the full operating range of the next stage.
A block diagram of the subranging architecture is shown in figure 1 where a 6 bit two stage adc is shown. Pipeline adc block diagram idea. The pipelined adc had its origins in the subrangingarchitecture which was first used in the 1950s as a means to reduce the component count and power in tunnel diode and vacuum tube flash adcs see references 1 2.
Pipelined adc with four 3 bit stages each stage resolves two bits.
10bit adc can be built with series of 10 adcs each 1 bit only each stage performs coarse a d conversion and computes its quantization error or residue stage 1 b 1bits digital output b 1. Adc1 module block diagram an5 an42 ivref ivtemp six stage conversion pipeline six digital comparators six digital result registers reference selection vrefh vrefl avdd sample and hold 1 dedicated an1 an46 an6. Design described in this report implements 9 stage pipelined architecture with 1 5 bits per stage. 10bit adc can be built with series of 10 adcs each 1 bit only each stage performs coarse a d conversion and computes its quantization error or residue stage 1 b 1bits digital output b 1.
