Sr Latch Timing Diagram. In this video i have solved an example on sr latch timing diagram. Following the convention the prime in s and r denotes that these inputs are active low.
February 6 2012 ece 152a digital design principles 25 the gated sr latch cont. In this video i have solved an example on sr latch timing diagram. A set state when q 1 or a reset state when q 0.
Shown in figure 4 a.
In addition to the two outputs q and q there are two inputs s and r for set and reset respectively. In this video i have solved an example on sr latch timing diagram. Shown in figure 4 a. In addition to the two outputs q and q there are two inputs s and r for set and reset respectively.
