Sr Latch Timing Diagram Explanation. In addition to the two outputs q and q there are two inputs s and r for set and reset respectively. This simple flip flop is basically a one bit memory bistable device that has two inputs one which will set the device meaning the output 1 and is labelled s and one which will reset the device meaning the output 0 labelled r.
When output q 1 and q 0 the latch is said to be in the set state. The sr latch constructed using two cross coupled nor gates is shown in fig 1. It is a clocked flip flop.
By using nand latch.
In this video i have solved an example on sr latch timing diagram. During period c both s and r are high causing the non allowed state where both outputs are high. 5 2 6 shows a timing diagram describing the action of the basic rs latch for logic changes at r and s. At time a s goes high and sets q which remains high until time b when s is low and r goes high resetting q.
