Successive Approximation Register Circuit Diagram. Instead of counting up in binary sequence this register counts by trying all values of bits starting with the most significant bit and finishing at the least significant bit. This adc is ideal for applications requiring a resolution between 8 16 bits.
Successive approximation register method sar is the most widely used method in a d conversion. One of the most common analog to digital converters used in applications requiring a sampling rate under 10 msps is the successive approximation register adc. This adc is ideal for applications requiring a resolution between 8 16 bits.
The circuit diagram is shown below.
Each channel can be sampled with a different sampling time. Synchrounous generally refers to something which is cordinated with others based on time synchronous signals occur at same clock rate and all the clocks follow the same reference clock. The difference is in the sar register converges on the digital equivalent. Instead of counting up in binary sequence this register counts by trying all values of bits starting with the most significant bit and finishing at the least significant bit.
